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OKI Semiconductor ML70512
Bluetooth Baseband Controller IC
FEDL70512-04
Issue Date: Sep. 2, 2003
GENERAL DESCRIPTION
The ML70512 is a CMOS digital IC for use in 2.4 GHz band BluetoothTM systems. This IC incorporates the ARM7TDMI as the CPU core, features a highly expandable architecture, and supports the interfaces for a variety of applications. Since the ML70512 has Oki's Bluetooth protocol stack software installed, when the IC is used in conjunction with the Bluetooth RF transceiver IC, data/voice communications are possible while maintaining interconnectivity with other Bluetooth systems.
FEATURES
* Conforms to Bluetooth Specification (Ver1.1) * Designed for connection with the RF-LSI interface, such as the OKI RF-LSI interface (ML7050, ML70561), the SKYWORKS RF-LSI interface (CX72303), or the BROADCOM RF-LSI interface (BCM2002X) that functions as the Bluetooth RF-LSI interface * The high-speed, low-power ARM7TDMITM is installed as the CPU core * PCM-CVSD transcoder that provides high quality voice using the noise filter is installed * Low power consumption in flexible power management modes according to operating modes of Bluetooth * DETACH signal provides control of change to power-saving mode (STOP) and return request to normal mode. * UART interface corresponding to baud rates up to 921.6 kbps * I2C bus interface provides accesses to EEPROM or PCM-Codec * Selactable 12 MHz, 13 MHz, or 16 MHz for the system clock * Selectable 32 kHz or 32.768 kHz for the LPO clock * Built-in programmed ROM eliminates external ROM/FLASH * The packages are available in two types: 83-pin WCSP for ML70512HB 84-pin BGA for ML70512LA
ARM, ARM7TDMI and Thumb are registered trademarks of ARM Ltd., UK. BLUETOOTH is a trademark owned by Bluetooth SIG, Inc. and licensed to Oki Electric Industry. The information contained herein can change without notice owing to the product being under development.
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SPECIFICATIONS
Process Package 0.16 m CMOS (5-layer metal wire) 83-pin WCSP (P-VFLGA83-6.22x6.22-0.50-W) (Dimensions: 6.22 mm x 6.22 mm x 0.48 mm; pin pitch: 0.50 mm) 84-pin BGA (P-LFBGA84-0909-0.80) (Dimensions: 9 mm x 9 mm x 1.5 mm; pin pitch: 0.80 mm) 23.4 mA (24 MHz operation) 2.70 to 3.6 V for input-output, 1.65 to 1.95 V for internal circuits 24 MHz 384 KB (for ARM program) 72 KB 12 MHz, 13 MHz, or 16 MHz (system clock) 32 kHz or 32.768 kHz (LPO clock) OKI RF-LSI interface (ML7050, ML70561) SKYWORKS RF-LSI interface (CX72303) BROADCOM RF-LSI interface (BCM2002X) UART interface (up to 921.6 Kbps) General-purpose I/O interface (Bits 0 and 1 are used as a pin for I2C bus interface depending on software installed) PCM interface (PCM Linear/A-law/-law can be selected) DETACH interface 16-bit auto reload timer (1ch) 18-bit auto reload timer (3ch) 11 causes Crystal oscillator circuit (12 MHz, 13 MHz, or 16 MHz, 32 kHz or 32.768 kHz) Internal PLL
Supply current Operating voltage ranges Operating frequency Built-in ROM size Built-in RAM size Input clocks RF-LSI interface
Installed interfaces
Timers Interrupt controller Clock control circuit
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PIN PLACEMENT
ML70512HB: 83-pin WCSP (P-VFLGA83-6.22 x 6.22-0.50-W)
GND
10
SCLKO
Core VDD PCM OUT GND Core VDD VDD
PCM SYNC PCM CLK GND
Core VDD CIO5 PCMIN
GND CIO0 (SCL) VDD
Core VDD CIO1 (SDA)
GND CIO4
RTS
RFSEL2
GND
9
GND CIO3 SIN
RFSEL0 GND
Core VDD
8
CIO2 RFSEL1 DETACH RESET GND SCLKN VDD
GND
7
SFRQ CIO6 SEL1
6
CTS AGND0 SCLKP AVDD0 AGND0 Core VDD
GND
5
SOUT PLL_ CLK PLL_ POW
LVDD RSSI _CLK Core VDD GND GND GND SFRQ SEL0
VDD
4
AVDD1 AGND1 AVDD0 PLL AVDD1 AGND1 LOCK VDD GND Core VDD
PLL_ DATA
3
PLL_ OFF
2
RX_ POW PLL_PS GND RXD
RSSI Core VDD
GND
TX_ POW PLL_LE TXD
1
VDD
SCLK VDD XC32KN SEL XC32KP
A
B
C
D
E
F
G
H
J
K
TOP VIEW
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ML0512LA: 84-pin BGA (P-TFBGA84-0909-0.80)
GND
10
Core AVDD1 AGND1 AVDD0 AGND0 SCLKN RESET RFSEL0 VDD RFSEL2 VDD GND CIO4 CTS RTS CIO2
XC32KP AVDD1 AGND1 AGND0 GND
9
VDD
8
SCLK XC32KN SEL AVDD0 VDD SFRQ SEL0 VDD RSSI
Core VDD SCLKP DETACH RFSEL1 GND CIO0 (SCL) CIO5
GND
7
Core CIO1 VDD (SDA) GND VDD Core VDD PCM SYNC Core VDD GND
Core VDD
6
GND PLL LOCK GND
RXD
5
PCMIN GND PCMCLK PCM OUT VDD NC CIO6 SFRQ SEL1 SIN Core VDD SCLKO GND Core VDD CIO3 NC GND
TXD
4
GND
PLL_LE PLL_PS PLL_ DATA
3
TX_ POW
2
RX_ POW PLL_ OFF
RSSI_ CLK PLL_ CLK
LVDD
VDD
PLL_ POW
1
GND
SOUT
GND
GND
VDD
A
B
C
D
E
F
G
H
J
K
TOP VIEW
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PIN DESCRIPTIONS
RF I/F
Pin Name Direction [*0] Internal Pull Up/ Down, Schmitt -- Initial Value L L L L -- -- -- -- X H L L L L L L L H PLL_LE O -- L B1 A3 Pin Placement Description ML70512HB ML70512LA ML7050: Transmit data output CX72303: Transmit data output BCM2002X: Transmit data output ML70561: Transmit data output ML7050: Receive data input CX72303: Receive data input BCM2002X: Receive data input ML70561: Receive data input ML7050: Serial write data CX72303: Serial write data BCM2002X: Transmit enable ML70561: Transmit enable (Active H) ML7050: Serial clock CX72303: Serial clock BCM2002X: Serial clock ML70561: Serial clock ML7050: Serial road enable 0: Negate, 1: Assert CX72303: Serial enable 0: Assert, 1: Negate BCM2002X: RF-LSI synthesizer on 0: Negate, 1: Assert ML70561: RF-LSI synthesizer on 0: Negate, 1: Assert ML7050: Receive field strength data input CX72303: Serial read data BCM2002X: Serial read data ML70561: Serial read data ML7050: Receive field strength data clock CX72303: RF-LSI receiving characteristic control BCM2002X: System clock request ML70561: System clock request ML7050: Local PLL power control 0: Assert, 1: Negate CX72303: PA Power control 0: Negate, 1: Assert BCM2002X: Select serial transmit mode ML70561: Select serial transmit mode
TXD
O
C1
A4
RXD
I
--
D1
A5
PLL_DATA
O
--
A3
C3
PLL_CLK
O
--
B4
C1
L
RSSI
I
--
-- -- -- -- H
E2
C5
RSSI_CLK
O
--
L H H H
C4
C2
PLL_POW
O
--
L H H
B3
A1
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Pin Name
Direction [*0]
Internal Pull Up/ Down, Schmitt
Initial Value H
Pin Placement Description ML70512HB ML70512LA ML7050: Transmit enable 0: Assert, 1: Negate CX72303: Transmit enable 0: Negate, 1: Assert BCM2002X: Serial write data ML70561: Serial write data ML7050: Receive enable 0: Assert, 1: Negate CX72303: Receive enable 0: Negate, 1: Assert BCM2002X: Receive enable ML70561: Receive enable
TX_POW
O
--
L L L H
A1
A2
RX_POW
O
--
L L L
B2
B2
[*0]
"I" = Input, "O" = Output, "I/O" = Input/Output
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RF I/F
Pin Name Direction [*0] Internal Pull Up/ Down, Schmitt Initial Value L L PLL_PS O -- L L -- -- -- -- H PLL_OFF O -- -- L L A2 B1 C2 B3 Pin Placement ML70512H B Description ML70512LA ML7050: "L" CX72303: Power on reset 0: Assert (reset) 1: Negate BCM2002X: RF-LSI receiving characteristic control ML70561: SYNCWORD detection ML7050: -- CX72303: -- BCM2002X: 1MHz clock ML70561: Clock for 1 MHz transmit data ML7050: PLL loop control 0: Open loop 1: Closed loop CX72303: Diversity output BCM2002X: PA Power control ML70561: PA Power control
PLLLOCK
I
--
H3
B5
CLK and Configuration
Pin Name SCLKP SCLKN XC32KP XC32KN SCLKSEL Direction I O I O I Internal Pull Up/ Down, Schmitt -- -- -- -- -- Initial Value -- -- -- -- -- Pin Placement Description ML70512HB K6 J7 K1 H1 J1 ML70512LA F8 F10 A9 B8 C8 System clock (12/13/16 MHz) pins (Power level: CMOS level) Subclock pins (for oscillator) System clock frequency select pin L: Select CLK divided by internal PLL H: Select subclock System clock (SCLK) frequency select/ BCM crystal frequency select pins
SFRQSEL [1:0] 00 01 10 11 SCLK input frequency (RFSEL 101) 13 MHz 12 MHz 16 MHz Reserved BCM crystal frequency (RFSEL = 101) 19.68 MHz 19.2 MHz 19.8 MHz 13 MHz
SFRQSEL 0-1
I
--
--
*[1]
*[2]
RF-LSI select pins
RFSEL[2:0] 001 010 011 101 Others RF-LSI ML7050 (OKI) CX72303 (SKYWORKS) ML70561 (OKI) BCM2002X (BROSDCOM) Reserved
RFSEL 0-2
I
--
--
*[3]
*[4]
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CLK and Configuration
Pin Name RESET DETACH SCLKO Direction I I O Internal Pull Up/ Down, Schmitt Schmitt Schmitt -- Initial Value -- -- -- Pin Placement Description ML70512HB K8 J8 B10 ML70512LA G10 G8 H3 Hardware reset pin (Reset = L) Sleep pin (Sleep = L) System clock (12/13/16 MHz) output pins
[*1] [*2] [*3] [*4]
SFRQSEL0: G2; SFRQSEL1: A6 SFRQSEL0: C7; SFRQSEL1: F2 RFSEL0: J9; RFSEL1: H8; RFSEL2: K10 RFSEL0: H10; RFSEL1: H8; RFSEL2: K10
PCM I/F
Pin Name PCMOUT PCMIN PCMSYNC Direction O I I/O Internal Pull Up/ Down, Schmitt -- Pull up Pull down Pull down Initial Value L -- -- Pin Placement Description ML70512HB C9 E8 D10 ML70512LA J4 H5 K4 PCM data output PCM data input PCM sync signal (8 kHz), Initial setting: input (can be switched by an internal register) PCM clock (64 kHz/128 kHz) Initial setting: input (can be switched by an internal register)
PCMCLK
I/O
--
D9
H4
Note: The PCM sync signal (8 kHz) must be guaranteed at the accuracy of 50 ppm if the PCMSYNC pin is configured as an input.
UART I/F
Pin Name SOUT SIN RTS CTS Direction O I O I Internal Pull Up/ Down, Schmitt -- Schmitt -- -- Initial Value H -- -- H Pin Placement Description ML70512HB B5 B7 J10 H6 ML70512LA E1 F1 K9 J9 ACE transmit serial data ACE receive serial data ACE transmit data ready ACE transmit ready
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Port
Pin Name CIO0 (SCL) CIO1 (SDA) CIO2 CIO3 CIO4 CIO5 CIO6 Direction I/O I/O I/O I/O I/O I/O I/O Internal Pull Up/ Down, Schmitt -- -- -- -- -- -- -- Initial Value H -- -- L H -- -- Pin Placement Description ML70512HB F9 G9 G8 B8 H9 E9 B6 ML70512LA H7 K7 K8 H2 H9 H6 F3 I2C serial clock (output) I2C serial data (input) General port (initial state: input) General port (initial state: output) General port (initial state: output) General port (initial state: input) General port (initial state: input)
NC
Pin Name NC Direction -- Internal Pull Up/ Down, Schmitt -- Initial Value -- Pin Placement Description ML70512HB -- ML70512LA [*4] No connection
[*4] NC: E3, J3 Note: Do not wire under the NC pin.
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Power, GND
Pin Name VDD CoreVDD LVDD GND AVDD0 AVDD1 AGND0 AGND1 Direction -- -- -- -- -- -- -- -- Internal Pull Up/ Down, Schmitt -- -- -- -- -- -- -- -- Initial Value -- -- -- -- -- -- -- -- Pin Placement Description ML70512HB [*5] [*7] C5 [*9] [*11] [*13] [*15] [*17] ML70512LA [*6] [*8] D2 [*10] [*12] [*14] [*16] [*18] I/O power supply pin 2.70 to 3.6 V Power supply pin for internal circuit 1.65 to 1.95 V RF-I/O power suply pin (Same voltage to the VDD for RF-LSI) Digital block ground pin Analog block power supply pin 1.65 to 1.95 V Analog block ground pin
[*5] [*6] [*7] [*8] [*9] [*10] [*11] [*12] [*13] [*14] [*15] [*16] [*17] [*18]
VDD: A4, C6, F1, F8, G1, H2, K7 VDD: A8, B7, C6, D3, E2, F9, K1, K6 Core VDD: A8, C7, C10, D3, E1, E10, G10, K2, K5 Core VDD: A6, E8, G1, G3, J7, J10, K3, K5 GND: A5, A7, A9, A10, B9, C8, D2, D8, E3, F2, F3, F10, G3, H7, H10, J2, K9 GND: A7, A10, B4, B6, C4, D1, E9, G2, G9, H1, J1, J2, J5, J6, J8, K2 AVDD0: H5, K4 AVDD0: D8, D10 AVDD1: H4, J3 AVDD1: B9, B10 AGND0: J5, J6 AGND0: D9, E10 AGND1: J4, K3 AGND1: C9, C10
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BLOCK DIAGRAM
CLK GEN Timer System Control APB Ctl AHB Ctl AMBA AHB I/F APB Ctl I/F AMBA APB I/F I/F PCM/ CVSD GPIO BT-BB Core I/F I/F UART I/F DETACH IF I/F Timer2 (3ch) IRC Arbiter TIC Default Slave 72KB RAM 384KB ROM IRAMC IROMC ARM7 TDMI
Default Slave
Clock AMBA APB Processor Bus
ML70512
RFLSI
I/F CTL/ WDT
DETACH
GPIO I/F
UART I/F
PCM Codec
FEDL70512-04
ML70512
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DESCRIPTION OF INTERNAL BLOCKS
CLKGEN Block * Generates a clock that is supplied to each block through SCLKP (12/13/16 MHz) * STOP/HALT function CTL/WDT Block * * * * * Control of the frequency division function of the internal main clock Control of clock supplied to each peripheral Control of reset of each peripheral STOP/HALT control Watchdog timer function (interrupt/reset)
Timer Block * * * * 3 channels 18-bit timer counter Interrupt by compare function One shot, interval, or free-run mode
Base band Core Block
RF LSI Tx SCO Buffer Audio Codec I/F Tx ACL Buffer Packet Composer TXD
Security APB ARM I/F Rx SCO Buffer Rx ACL Buffer
Timing
FHCNT
RF CNT
CNT
Packet Decomposer
RXD
* RF Controller - RF power supply control (PLL, TX, RX) - Local PLL frequency division ratio setting - Receive clock regeneration function - Synchronization detection (synchronizing within the permissable error limit of SyncWord) - Receive clock re-timing function * FH Controller hopping - Sequence control - Frequency hopping selection function - CRC computation's initial value selection function
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* Timing Generator - Bluetooth clock generation - Operation interrupts depend on mode (slot, scan, sniff, hold, park) - Sync detection timing generation (sync window 10 s) - PLL setting timing generation - Transmit/Receive timing generation - Multi-master timing management function * Packet Composer - Access code generation (SyncWord generation, appending PR*TRAILER) - Packet header generation (HEC generation, scrambling, FEC encoding) - Payload generation (CRC generation, encryption, scrambling, FEC encoding) - Packet synthesis * Packet Decomposer - Packet decomposition (separating the packet header and the payload) - Packet header processing (FEC decoding, descrambling, HEC error detection, header information separation) - Payload processing (FEC decoding, descrambling, encryption decoding, CRC judgement, payload separation) * Security - Various key generation functions (initialization, link key, encryption key) - Certification function - Encryption function
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UART Block * * * * * * * * * * Full-duplex buffering method All status reporting function Built-in 64-byte transmit/receive FIFO Modem control based on CTS Programmable serial interface 5-, 6-, 7-, 8-bit characters Generation and verification of odd parity, even parity, or no parity 1, 1.5, or 2 stop bits Programmable Baud Rate Generator (9600 bps to 921.6 kbps) Error servicing for parity, overrun, and framing errors
* Configuration of 1 Data Frame during Reception
SIN SAMPLE CLK
5 data bits to 8 data bits
Start
Parity
Stop
* Configuration of 1 Data Frame during Transmission
SOUT
Start 5 data bits to 8 data bits Parity Stop
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PCM-CVSD Transcoder Block * Application side I/O: - PCM Codec * Application-side format: - PCM linear (8, 14, 16 bits/sample, 8 kHz sampling frequency)/A-law/-law * Bluetooth-side format: - CVSD/A-law/-law * All combinations of the above conversions are supported * PCMSYNC/PCMCLK I/O can be switched (initial setting: input) * Timing in Short Mode and in PCMCLK and PCMSYNC Output Mode (For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)
8 bits or 16 bits PCMCLK(O)
64k/128kHz
PCMOUT
LSB
MSB
DATA
DATA
DATA
LSB
MSB
DATA
Data is output on the rising edge of CLK. PCMIN PCMSYNC(O) LSB MSB DATA DATA DATA LSB MSB DATA
Data is shifted in on the falling edge of CLK
125s (8kHz)
* Timing in Short Mode and in PCMCLK and PCMSYNC Input Mode. (For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)
8 bits or 16 bits PCMCLK(I)
64k/128kHz
PCMOUT
LSB
MSB
DATA
DATA
DATA
LSB
MSB
DATA
Data is output on the rising edge of CLK. PCMIN PCMSYNC(I) LSB MSB DATA DATA DATA LSB MSB DATA
Data is shifted in on the falling edge of CLK
125s (8kHz)
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* Timing in Long Mode and in PCMCLK and PCMSYNC Output mode (For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)
8 bits or 16 bits
PCMCLK(O)
64k/128kHz
PCMOUT
MSB
DATA
DATA
DATA
DATA
LSB
MSB
DATA
Data is output on the rising edge of CLK PCMIN PCMSYNC(O) PCMCLK period x 3 125s (8kHz) MSB DATA DATA DATA
Data is shifted in on the falling edge of CLK DATA LSB MSB DATA
* Timing in Long Mode and in PCMCLK and PCMSYNC Input Mode. (For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)
8 bits or 16 bits
PCMCLK(I)
64k/128kHz
PCMOUT
MSB
DATA
DATA
DATA
DATA
LSB
MSB
DATA
Data is output on the rising edge of CLK. PCMIN MSB DATA DATA DATA
Data is shifted in on the falling edge of CLK. DATA LSB MSB DATA
PCMCLK period (Min.) or 62.5 s (Max.) 125s (8kHz)
DETACH Interface Block * Generation of the request for change to (from) the stop mode by detection of the rising (falling) edge of the DETACH signal * Generation of the request for restore from the stop mode by detection of a SIN signal level change
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ABSOLUTE MAXIMUM RATINGS
Parameter I/O power supply voltage Core power supply voltage Input voltage Allowable power dissipation Storage temperature Symbol VDD/LVDD CoreVDD/AVDD VI Pd Tstg Conditions -- -- -- -- -- Rating -0.3 to +4.5 -0.3 to +2.5 -0.3 to +4.5 0.62 -55 to 150 Unit V V V W C
RECOMMENDED OPERATING CONDITIONS
Parameter I/O power supply voltage Core power supply voltage "H" level input voltage "L" level input voltage Operating temperature Symbol VDD/LVDD CoreVDD/AVDD Vih Vil Ta Conditions -- -- -- -- -- Min. 2.7 1.65 2.2 0 -40 Typ. 3.3 1.8 -- -- -- Max. 3.6 1.95 VDD 0.8 85 Unit V V V V C
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter "H" level output voltage "L" level output voltage Input leakage current (VDD = 2.7 to 3.6 V, CoreVDD = 1.65 to 1.95 V, Ta = -40 to +85C) Symbol Conditions Min. Typ. Max. Unit Ioh = 3.0VVdd3.6V 2.4 -- -- Voh V -2 mA 2.7VVdd<3.0V 2.2 -- -- Vol Iol = 2 mA Vi = GND to 3.6 V Vi = VDD 50 k Pull-down Vi = GND 50 k Pull-up Vo = GND to VDD Vo = VDD 50 k Pull-down During 24 MHz operation CLK stopped -- -10 10 -200 -10 10 0 -- -- -- 66 -66 -- 66 23.4 50 0.4 10 200 -10 10 200 33 250 A V
Ii
A
Output leakage current Io Power supply current (during operation) Power supply current (during stand-by)
Iddo Idds
mA A
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Power Supply Current (IDDO) Characteristics by Power Saving Mode
(VDD = 2.7 V to 3.6V, CoreVDD = 1.65 V to 1.95V, Ta = -40 to 85C) Operating mode Conditions Min. Typ. Max. Unit STOP mode (DETACH = "L") -- -- 0.05 -- Interval:1.28sec -- 1.5 -- Page Scan operating mode Window:22.5msec Poll Interval operating mod Interval:40slot -- 12.1 -- Interval:2000slot -- 1.7 -- Sniff operating mode Attempt:4frame mA Hold operating mode Interval:4000slot -- 4.9 -- DH1/DM1 -- 23.4 -- RX:DH3/DM3 -- 20.5 -- ACL operating mode TX:DH1/DM1 RX:DH5/DM5 -- 19.6 -- TX:DH1/DM1
AC Characteristics System clock (SCLKP) SCLKP
Tmc0 Tmc1
Parameter Tmc0 Tmc1
(VDD = 2.7 to 3.6V, CoreVDD = 1.65 to 1.95V, Ta = -40 to 85C) Description Min Typ Max Unit Duty in SCLKP "H" duration 40 50 60 % Duty in SCLKP "L" duration 40 50 60 %
Sub-clock (XC32KP)
XC32KP
Tmp0 Tmp1
Parameter Tmp0 Tmp1
(VDD = 2.7 to 3.6V, CoreVDD = 1.65 to 1.95V, Ta = -40 to 85C) Description Min Typ Max Unit Duty in XC32KP "H" duration 40 50 60 % Duty in XC32KP "L" duration 40 50 60 %
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Reset
Power supply stable period
Vdd/LVdd
CoreVdd/AVdd
TRESW RESET
Parameter TRESW
Reset pulse width
(VDD = 2.7 to 3.6V, CoreVDD = 1.65 to 1.95V, Ta = -40 to 85C) Description Min Typ Max Unit 10 -- -- s
Note : Apply "L" to the RESET pin for 10 sec or more after the power supply has been settled.
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PCM interface
PCMCLK(I) PCMIN
Tpc0 Tpc1 Tpc2
PCMOUT
Tpc2
PCMSYNC(I)
Tpc3 Tpc4 Tpc3 Tpc4
PCMCLK(O) PCMIN
Tpc5 Tpc6
PCMOUT
Tpc 7 Tpc7
PCMSYNC(O)
Tpc 8
Parameter Tpc0 Tpc1 Tpc2 Tpc3 Tpc4 Tpc5 Tpc6 Tpc7 Tpc8
(Vdd = 2.7 to 3.6V, CoreVdd = 1.65 to 1.95V, Ta = -40 to 85C) Description Min Typ Max Unit PCMIN setup time relative to PCMCLK (input) falling edge 100 -- -- ns PCMIN hold time relative to PCMCLK (input) falling edge 100 -- -- ns PCMOUT delay time relative to PCMCLK (input) rising edge -- -- 250 ns PCMSYNC (input) setup time relative to PCMCLK (input) 100 -- -- ns rising edge PCMSYNC (input) hold time relative to PCMCLK (input) 100 -- -- ns rising edge PCMIN setup time relative to PCMCLK (output) falling edge 100 -- -- ns PCMIN hold time relative to PCMCLK (output) falling edge 100 -- -- ns PCMOUT delay time relative to PCMCLK (output) rising -- -- 250 ns edge Delay time from PCMCLK (output) rising edge to PCMSYNC -- -- 150 ns (output)
AC Characteristic Measuring Points
VDD 0.8VDD 0.2VDD 0.8VDD 0.2VDD
0V
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REFERENCE FOR VOLTAGE SUPPLY CIRCUIT
ML70512
AVDD0 0.1F AGND0 AVDD1 0.1F AGND1
CoreVDD
10 to 47F
0.1F
0.1F
CoreVDD
LVDD
10 to 47F
0.1F
0.1F
VDD 10 to 47F GND 0.1F 0.1F
VDD GND
Capacitors should locate close to LSI pins.
Feed lines should be separated from LSI pins.
Example of ML70512 voltage supply circuit * Insert appropriate bypass capacitors between the VDD and GND lines. Note 1: Precautions to insert the bypass capacitors - Use traces of VDD and GND lines wider than those of the other signal lines. - Keep the length of traces between the bypass capacitors and the VDD line and between the bypass capacitors and the GND line as short as possible. - Keep the length of traces between the bypass capacitors and the VDD line and between the bypass capacitors and the GND line as equal as possible. The circuit is subject to change according to the specific LSI board design. Please contact Oki Electric Industry Co., Ltd. for detailed information.
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REFERENCE FOR OSCILLATOR CIUCUIT
ML70512
XC32KP
XC32KN
R0 R1
SCLKP
R2 R3
C0
X'tal 1
C1
C2
X'tal 2
SCLKN C3
Connect this oscillator circuit only when connecting the OKI RF-LSI ML7050.
Example of oscillator circuit Note 1: The values of C0 and C1, and R0 and R1 should be determined according to the specifications for the external crystal X'tal 1 (32 or 32.768 kHz). The values of C2 and C3, and R2 and R3 should be determined according to the specifications for the external crystal X'tal 2 (12, 13, or 16 MHz). Note 2: The crystal oscillator circuit should be connected to pins SCLKP and SCLKN only when the OKI RF-LSI (ML7050) is connected. In other cases, the system clock should be input from the RF-LSI to pin SCLKP. Note 3: In the case of 12 MHz, 13 MHz, or 16 MHz system clock (SCLKP) input, make sure the crystal frequency tolerance is 20 ppm for temperature, supply voltage, and aging. In the case of 32 kHz or 32.768 kHz sub-clock (XC32KP) input, make sure the crystal frequency tolerance is 250 ppm for temperature, supply voltage, and aging. Note 4: Precautions to build a crystal oscillator circuit - Keep length of wire traces as short as possible. - Do not cross the crystal oscillator circuit wires over other signal line wires. - Do not keep signal line wires through which high current flows close to the crystal oscillator circuit. - Keep the grounding point of the capacitors in the oscillator circuit at the potential equal to GND. And do not connect the capacitors to the GND or GND lines through which high current flows. - Do not output signals from the oscillator circuit. The circuit is subject to change according to the specific LSI board design. Please contact Oki Electric Industry Co., Ltd. for detailed information. It is recommended to determine the final circuit values including the capacitance of the circuit board designed by the user.
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ML70512
APPLICATION NOTES
Clock Selection * The system clock frequency is selected according to external pin SFRQSEL. SFRQSEL = 00 SFRQSEL = 01 SFRQSEL = 10 : : : A 13 MHz clock is input to external pin SCLKP. A 12 MHz clock is input to external pin SCLKP. A 16 MHz clock is input to external pin SCLKP.
A 12 MHz clock is input to external pin SCLKP regardless of SFRQSEL when BCM2002X is selected (RFSEL = 101). * The CPU clock supply source is selected according to external pin SCLKSEL. SCLKSEL = 0 : Use the clock that was divided down from the internal PLL output of 192 MHz that was generated from external pins SCLKP. (Dividing ratios are selectable in the range of 1/6 to 1/16. Initial value is 1/8 (24 MHz).) : Use external pins XC32KP.
SCLKSEL = 1
Note: The clock supply source can be set by the CLKCNTL register in the CTL/WDT block once the LSI is powered up. * The frequency of CPU clock is selectable from the high speed (24 MHz) and low speed (16 MHz). This can be performed by the Vendor Specific Command. Setting the Reset * Apply "L" level to the RESET pin for more than 10 s after power voltage is stabilized. When the system clock oscillator circuit is stable and the RESET pin is at "H" level, the internal reset is released and operation starts after the internal reset is held for 1.9 ms for the input clock of 13 MHz, 2.0 ms for the input clock of 12 MHz, or 1.5 ms for the input clock of 16 MHz. Moreover, after power voltage is stable, the values of SCLKSEL, SFRQSEL0-1, and RFSEL0-2 should be determined before the RESET pin is at "H" level. Setting the UART Baud Rate * It is possible to set the UART baud rate using the Vendor Specific Commands. Available baud rate settings: 9600/19.2k/38.4k/56k/57.6k/115.2k/230.4k/345.6k/460.8k/921.6k (Initial value is 115.2 kbps.) Setting the PCM-CVSD Transcoder * It is possible to set the PCM-CVSD transcoders using the Vendor Specific Commands. For command details, contact Oki Electric Industry Co., Ltd.
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* It is possible to set the following parameters using the VCCTL command: - PCMSYNC/PCMCLK mode (initial setting: input) - Mute reception (initial setting: OFF) - Mute transmission (initial setting: OFF) - Aircoding CVSD (initial setting)/-law/A-law - Interface coding Linear (initial setting)/-law/A-law - PCM format (data width of one PCM Linear sample) 8-bit (initial setting)/14-bit/16-bit - Serial interface format Short frame (initial setting)/long frame - Application interface mode PCM Codec I/F (initial setting)/APB I/F XTAL Input Frequency of BCM2002X * If the system clock is supplied from BCM2002X, the XTAL input frequency of BCM2002X must be 13, 19.2, 19.68, or 19.8 MHz. 12 MHz should not be applied. XTAL Input Frequency of CX72303 * If the system clock is supplied from CX72303, the XTAL input frequency of CX72303 must be 13 MHz. 10 MHz should not be applied. Required processes when interface pins are unused * The following tables show the processes that should be performed when interface pins are not used. * The pins that are not included in the following table should be left open. RF I/F
Pin Name RXD RSSI PLLLOCK Process When Pin Not Used GND GND GND Comments
UART I/F
Pin Name SIN CTS Process When Pin Not Used VDD GND Comments
PCM I/F
Pin Name PCMIN PCMSYNC PCMCLK Process When Pin Not Used Open or VDD Open or GND Open or GND Comments
Processes of Other Pins TEST I/F etc.
Pin Name DETACH Process When Pin Not Used Pull up or VDD Comments
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VDD
System Configuration Example ML70512/ML7050
ML70512 ML7050 VDD_D ANT RESET
47 0.1 0.1 RFVDD VDD
LVDD
Poewr on reset
GND
68k
OKI Semiconductor
Hardware reset
Microphone PCMOUT PCMIN PCMSYNC PCMCLK
GND
Voice input/ output peripherals MSM7702-01 MCLK
Speaker
PCMIN PCMOUT RSYNC XSYNC BCLK
RXD PLL_LE PLL_DATA PLL_CLK PLL_OFF TXD PLL_POW RX_POW TX_POW RSSI RXD PLL_LE PLL_DATA PLL_CLK PLL_OFF TXD PLL_POW RX_POW TX_POW
SCLKSEL
GND GND
RSSI_CLK PLL_PS PLLLOCK SCLKO SCLKN
13MHz 20ppm
SFRQSEL1 SFRQSEL0
GND
VDD
VDD
RFSEL2 RFSEL1 RFSEL0 SCLKP XC32KN DETACH AVDD0
0.1 32kHz or 32.768kHz 250ppm GND GND GND
68k
XC32KP
AGND0 AVDD1
0.1
TD RTS
Separate, as far as possible, the wiring from the board pins.
AGND1
VDD
SOUT RTS SIN CTS CIO6 CIO5
VDD
UART I/F
T1IN T1OUT T2IN T2OUT T3IN R1OUT R1IN R2OUT R2IN
GND RD CTS
CoreVDD
GND
DSUB9PIN MAX3245
GND VDD VDD 47k GND
VDD 0.1 47
CoreVDD CIO4(LED1) VDD GND NC CIO3(LED0) CIO2 SDA(CIO1) SCL(CIO0)
0.1
1 2 3 4 5 6 7 8 9
0.1
0.1
47
SDA SCL
Vcc
GND
The capacitors should be as close to the LSI pins as possible.
GND AT24C02
GND
FEDL70512-04
ML70512
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FEDL70512-04
OKI Semiconductor
ML70512
PACKAGE DIMENSIONS
ML70512HB - 83pinWCSP (P-VFLGA83-6.22 x 6.22-0.50-W)
(Unit: mm)
P-VFLGA83-6.22x6.22-0.50-W
5
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin Sn/Pb Solder plating (5m) 0.04 TYP. 1/July 5, 2002
Note: A lead-free package is available. Please contact Oki Sales Office/Distributors for more information.
Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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OKI Semiconductor
ML70512
ML70512LA - 84pin BGA (P-LFBGA84-0909-0.80)
(Unit: mm)
P-LFBGA84-0909-0.80
5
Package material Ball material Package weight (g) Rev. No./Last Revised
Epoxy resin Sn/Pb 0.20 TYP. 1/May 15, 2000
Note: A lead-free package is available. Please contact Oki Sales Office/Distributors for more information.
Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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FEDL70512-04
OKI Semiconductor
ML70512
REVISION HISTORY
Document No. FEDL70512-01 Date Feb. 17, 2003 Page Previous Current Edition Edition --FEDL70512-02 Mar. 18, 2003 23 -FEDL70512-03 Apr. 8, 2003 18 2 17 FEDL70512-04 Sep. 2, 2003 18 18 18 2 17 23 ---Final edition 1 Final edition 2 Eliminated the "RESET" row in the table of the "TEST I/F " Section. Final edition 3 Partially eliminated the contents of "Reset" Section. Partially eliminated the "SPECIFICATIONS" Section. contents of Description
Partially eliminated the contents of "DC Characteristics" Section. Partially eliminated the contents of "Power Supply Current (IDDO) Characteristics by Power Saving Mode" Section. Partially eliminated the contents of "Setting the Reset" Section.
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FEDL70512-04
OKI Semiconductor
ML70512
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2003 Oki Electric Industry Co., Ltd.
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